Open Issues Need Help
View All on GitHubRISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
AI Summary: This issue proposes adding support for the Svinval extension, which introduces three new instructions for fine-grained TLB invalidation. In an emulator context, these instructions can be simplified to existing coarser TLB flushes or no-ops. The implementation involves updating the instruction table, decoder, and execution logic to handle these new opcodes with their specified emulator behaviors.
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
AI Summary: This issue requests adding Zihpm (hardware performance monitor counters) support, which is part of the RVA22 specification. For an emulator, this primarily involves ensuring that accesses to a specific range of `hpmcounter` and `mhpmevent` CSRs do not trap, instead returning 0 on read and silently ignoring writes. Key tasks include adding these CSR numbers, modifying the CSR dispatch logic to prevent illegal instruction traps for them, and implementing `mcounteren`/`scounteren` for proper U/S-mode access control.
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
AI Summary: This GitHub issue proposes adding support for three RISC-V cache block operation extensions (Zicbom, Zicbop, Zicboz) to an emulator. Most instructions from these extensions, such as cache management and prefetch hints, can be implemented as no-ops. The primary exception is `cbo.zero` from Zicboz, which requires actually zeroing a memory block.
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
AI Summary: This issue proposes adding the Zbs (single-bit manipulation) extension, which is part of the larger RVA22 support effort. It introduces eight new instructions, including `bclr`, `bext`, `binv`, and `bset`, each with R-type (register-indexed bit) and I-type (immediate bit) variants. The issue provides precise encodings and operational definitions for each instruction, simplifying implementation.
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
AI Summary: This GitHub issue describes an investigation into the `Emulator::tick()` function, specifically the parameter passed to it (e.g., `self.tick(40)`). This parameter controls the coupling between the emulated CPU and other system functions. The user experimented with various values to characterize a known bug where certain parameters cause the emulated Linux to hang, documenting different boot behaviors and specific freeze points.
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more
RISC-V RV64GC SoC emulator, cli and browser; boots Debian and more