shsridhar-beep/svgap

Good first issue: add a troubleshooting and doctor guide to the docs about 8 hours ago

good first issue

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add a finding-ID reference table to the docs about 8 hours ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: validate every packaged taskpack manifest in a test about 8 hours ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add negative fixtures for a malformed intent manifest about 8 hours ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add `svgap demo --scenario all` to run every scenario about 8 hours ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add a power-on-state demo scenario about 8 hours ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add a minimal annotated intent-manifest example to the docs 1 day ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: list available demo scenarios from the CLI 1 day ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add a clock-domain-crossing demo scenario 1 day ago

good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add a combinational-crossing demo scenario 8 days ago

enhancement help wanted good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: document Linux tool installation and doctor failures about 1 month ago

documentation help wanted good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add a minimal disputed-finding regression fixture about 1 month ago

help wanted good first issue oracle-review

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add negative fixtures for the result registry schema about 1 month ago

help wanted good first issue research

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Good first issue: add a copy-paste JSON demo example about 1 month ago

documentation help wanted good first issue

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Add a public benchmark functional-result adapter about 1 month ago

help wanted research

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Contribute additional reset-release task families for v0.3 about 1 month ago

help wanted task-pack research

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Add a second open-source SystemVerilog frontend about 1 month ago

help wanted backend

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

Export normalized findings as SARIF and static HTML about 1 month ago

enhancement help wanted

shsridhar-beep/svgap

0

Structural-validity evaluation for AI-generated RTL

Python

#ai-evaluation#cdc#eda#hardware-verification#rdc#systemverilog#verilog

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