riscv

riscv/riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

120 stars 53 forks 120 watchers Python Creative Commons Attribution 4.0 International
capabilities compartmentalization memory-safety
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3 Open Issues Need Help Last updated: Sep 17, 2026

Open Issues Need Help

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pointer masking and executable memory 6 days ago
help wanted Important but after v1.0 ratification
riscv/riscv-cheri
120

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Python
#capabilities#compartmentalization#memory-safety
Vector indexed loads with 0 base and XLEN offsets 12 months ago
help wanted Important but after v1.0 ratification
riscv/riscv-cheri
120

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Python
#capabilities#compartmentalization#memory-safety
Should C.ADD(I) be C.CADD(I) in capability mode? about 1 year ago
enhancement help wanted question ratification blocker unpriv cheri spec
riscv/riscv-cheri
120

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Python
#capabilities#compartmentalization#memory-safety