llvm/circt

[ImportVerilog] Streaming operators fail on unpacked arrays 12 days ago

good first issue ImportVerilog

llvm/circt

2.2K

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#circt#llvm#mlir

[Moore] Missing conversions to open array types 13 days ago

good first issue Moore

llvm/circt

2.2K

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#circt#llvm#mlir

[MooreToCore] DPI calls with open array arguments are broken 14 days ago

good first issue Moore

llvm/circt

2.2K

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#circt#llvm#mlir

[Comb] ICmp folds missing for CEQ/CNE/WEQ/WNE 17 days ago

good first issue Comb

llvm/circt

2.2K

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#circt#llvm#mlir

`-DMLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON` might have found some invalid API usages 28 days ago

help wanted FIRRTL Handshake HW LLHD Calyx Comb Arc LoopSchedule

llvm/circt

2.2K

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#circt#llvm#mlir

[FIRRTL] Export Literal Identifiers Correctly 3 months ago

good first issue FIRRTL

llvm/circt

2.2K

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[FSM] Tracking issue for canonicalization and optimization patterns 4 months ago

help wanted FSM

llvm/circt

2.2K

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[CI] Include the Runner Version in the sccahe key (hashed or as a string) 4 months ago

good first issue CI/CD

llvm/circt

2.2K

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[FIRRTL][circt-reduce] Extend the FIRRTL LayerDisable reduction to strip enabled layers 4 months ago

good first issue FIRRTL Reducer

llvm/circt

2.2K

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#circt#llvm#mlir

[Synth][FunctionalReduction] Fold constants 4 months ago

good first issue Synth

llvm/circt

2.2K

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[FIRRTL] Implement folder/canonicalizer for muxcell intrinsics 5 months ago

good first issue FIRRTL

llvm/circt

2.2K

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[Synth][FunctionalReduction] Remove redundant reachable values from choice classes 5 months ago

good first issue Synth

llvm/circt

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[Synth][FunctionalReduction] Improve choice materialization with reachability of choice 5 months ago

good first issue Synth

llvm/circt

2.2K

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[Synth][FunctionalReduction] Add a newVar interface to SATSolver and use it in FR 5 months ago

good first issue Synth

llvm/circt

2.2K

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#circt#llvm#mlir

[Synth] Add a folder/canonicalization for synth.xor_inv 5 months ago

good first issue Synth

llvm/circt

2.2K

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[AIGERImporter] Support Bad state and Inveriants for Formal Verification application 5 months ago

good first issue Synth

llvm/circt

2.2K

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[Synth] Make passes runnable on any operation 5 months ago

good first issue Synth

llvm/circt

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[Synth] [LowerWordToBits] Constant defined outside of IsolatedAbove region 5 months ago

bug good first issue Synth

llvm/circt

2.2K

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[Synth][FunctionalReduction] Check inversion when creating equivalence class 5 months ago

good first issue Synth

llvm/circt

2.2K

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[Synth] Add canonicalization for choice 6 months ago

good first issue

llvm/circt

2.2K

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[FIRRTL] Replace redundant RewritePattern with OpRewritePattern 6 months ago

good first issue FIRRTL

llvm/circt

2.2K

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[Synth] Add folder/canonicalization to maj_inv 6 months ago

good first issue

llvm/circt

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[SV] Crash in `P/BPAssignOp` verifiers for `hw.inout` ports 7 months ago

bug good first issue Verilog/SystemVerilog

llvm/circt

2.2K

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[Seq] Register symbol with special characters does not round-trip 7 months ago

bug good first issue Seq

llvm/circt

2.2K

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[InferResets] Print field/signal names in diagnostic 7 months ago

AI Summary: The `InferResets` pass in CIRCT's FIRRTL dialect currently produces diagnostic messages that lack specific field, signal, or port names, making debugging difficult, especially with complex bundles or multiple resets. The proposed solution is to implement a `guessName(FieldRef fieldRef)` function that traverses the FIRRTL IR to construct a hierarchical name for the field, which can then be included in the diagnostic output to provide more helpful context to the user.

Complexity: 3/5

good first issue FIRRTL

llvm/circt

2.2K

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[FIRRTL] Improve Error Message on Uninferred Reset of Uninstantiated Module 7 months ago

enhancement good first issue

llvm/circt

2.2K

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