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hisi-riscv-rs
hispark-rs/hisi-riscv-rs
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3 Open Issues Need Help
Last updated: Jul 9, 2026
Open Issues Need Help
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C0: finish WS63 example-level HIL smoke (uart_hello/timer/gpio clock evidence)
27 days ago
help wanted
hardware
component:uart
priority: high
hispark-rs/hisi-riscv-rs
2
Rust
Deferred: BS2X deeper port (linx131 ISA / ROM startup / BLE-SLE connectivity)
27 days ago
help wanted
bs2x
component:ble
priority: medium
hispark-rs/hisi-riscv-rs
2
Rust
C3-C5: Wi-Fi scan → connect → ping demo + uart_echo on real silicon
27 days ago
enhancement
help wanted
connectivity
component:wifi
component:uart
priority: high
hispark-rs/hisi-riscv-rs
2
Rust