al-nafisah/fpga-project-analyzer - 8 Help Wanted Issues

Open Issues Need Help

`fpa show` prints generic names instead of values for pass-through overrides 4 days ago

bug good first issue

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq

`fpa show` lists only the first 24 generics 5 days ago

bug good first issue

al-nafisah/fpga-project-analyzer

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq

VHDL: register signals declared inside a generate block 5 days ago

bug good first issue

al-nafisah/fpga-project-analyzer

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq

Toolchain: Intel/Altera Quartus projects 6 days ago

help wanted toolchain

al-nafisah/fpga-project-analyzer

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq

Check: 2-FF synchronizer without ASYNC_REG 6 days ago

help wanted new-check

al-nafisah/fpga-project-analyzer

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq

Clock enables named like clocks are typed as clocks 6 days ago

bug good first issue

al-nafisah/fpga-project-analyzer

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq

VHDL: keep all generics of an entity, not the first 24 6 days ago

bug good first issue

al-nafisah/fpga-project-analyzer

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq

VHDL: evaluate generics and `if`/`for ... generate` conditions 6 days ago

enhancement help wanted

al-nafisah/fpga-project-analyzer

See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI coding agents.

Python

#agent-skills#ai-agents#cdc#claude-code#fpga#llm#mcp#mcp-server#pynq#rtl#systemverilog#verilog#vhdl#vivado#xilinx#zynq