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Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
help wanted asic
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
help wanted ci
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
help wanted fpga
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
documentation good first issue
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog