HUNT-001/ai-chip-design-platform - 4 Help Wanted Issues

Open Issues Need Help

CONTRIBUTING.md should require a test that fails before the fix 4 days ago

documentation good first issue

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog

Audit except Exception handlers that hide programming errors 4 days ago

good first issue silent-failure tech-debt

HUNT-001/ai-chip-design-platform

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog

Test fixtures are built from implementations, not schemas 4 days ago

enhancement help wanted test-gap

HUNT-001/ai-chip-design-platform

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog

Producers emit drifted status vocabulary at phase level 4 days ago

bug good first issue area: schema

HUNT-001/ai-chip-design-platform

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog